DK-DEV-5SGXEA7N【PDF 256/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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8-36

ALTCHIP_ID Megafunction

SV51010

2014.01.10

? Available in all configuration schemes except JTAG

? Supports both remote system upgrades and compression features

The Stratix V design security feature provides the following security protection for your designs:

? Security against copying — the security key is securely stored in the Stratix V device and cannot be read

out through any interface. In addition, as configuration file read-back is not supported in Stratix V devices,

your design information cannot be copied.

? Security against reverse engineering — reverse engineering from an encrypted configuration file is very

difficult and time consuming because the Stratix V configuration file formats are proprietary and the file

contains millions of bits that require specific decryption.

? Security against tampering — After you set the tamper protection bit, the Stratix V device can only accept

configuration files encrypted with the same key. Additionally, programming through the JTAG interface

and configuration interface is blocked.

When you use compression with the design security feature, the configuration file is first compressed and

then encrypted using the Quartus II software. During configuration, the device first decrypts and then

decompresses the configuration file.

When you use design security with Stratix V devices in an FPP configuration scheme, it requires a different

DCLK -to- DATA[] ratio.

ALTCHIP_ID Megafunction

The ALTCHIP_ID megafunction provides the following features:

? Acquiring the chip ID of an FPGA device.

? Allowing you to identify your device in your design as part of a security feature to protect your design

from an unauthorized device.

Related Information

ALTCHIP_ID Megafunction User Guide

JTAG Secure Mode

When you enable the tamper-protection bit, Stratix V devices are in the JTAG secure mode after power-up.

During this mode, many JTAG instructions are disabled. Stratix V devices only allow mandatory JTAG

1149.1 and 1149.6 instructions to be exercised. These JTAG instructions are SAMPLE/PRELOAD , BYPASS ,

EXTEST , and optional instructions such as IDCODE and SHIFT_EDERROR_REG .

To enable the access of other JTAG instructions such as USERCODE , HIGHZ , CLAMP , PULSE_nCONFIG , and

CONFIG_IO , you must issue the UNLOCK instruction to deactivate the JTAG secure mode. You can issue the

LOCK instruction to put the device back into JTAG secure mode. You can only issue both the LOCK and UNLOCK

JTAG instructions during user mode.

Related Information

? Supported JTAG Instruction on page 10-3

Provides more information about JTAG binary instruction code related to the LOCK and UNLOCK

instructions.

Altera Corporation

Configuration, Design Security, and Remote System Upgrades in Stratix V Devices

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